inSilica is positioned to engage with customers at any level of abstraction starting from product specifications to Netlist. Using a world class design team, diverse IP portfolio, a unique structured custom design methodology and a cost effective Tier One supply chain, inSilica is able to offer customers a diverse array of engagement scenarios.
inSilica supports three major engagement scenarios, namely Specification, RTL and Netlist.
Under this engagement scenario, the customer provides inSilica with the product requirements typically developed by the customer's product marketing and engineering groups.
Starting with the product requirements, inSilica will architect the device and deliver back to the customer a micro-architecture specification. Once the micro-architecture specification is approved inSilica will develop the RTL for this device and independently or jointly verify the design.
inSilica will assume responsibility for logic synthesis, custom hard macro development if that is required, physical design, and timing closure of the device. inSilica will manage all supply chain activities from procurement of 3rd party IP, first prototypes, and through to production.
Under this engagement scenario, inSilica will be responsible for the full RTL to tape-out flow. inSilica will complete all necessary tasks to procure, characterize, and process the appropriate standard-cell library, pad-cell library, hard-macro libraries, memories and register files. inSilica will review, evaluate, and make recommendations for RTL and SDC changes to accommodate DFT and other back-end related issues.
inSilica will generate ATPG vectors to achieve acceptable coverage of the un-collapsed, single-stuck-at, detectable faults in the random logic. Unobservable and uncontrollable faults will be excluded from the set of faults for the purposes of coverage calculation. Memories and register files will be covered using BIST.
inSilica will be responsible for all tasks related to the ATE testing of the customer device. These tasks include, test program generation incorporating the ATPG vectors and the functional vectors supplied by customer, test hardware development and procurement, wafer probing, and package testing.
inSilica will be responsible for package selection and procurement. Customer will review and sign-off on the package selection. inSilica will be responsible for prototype fabrication and delivery. Lastly, inSilica will be responsible for the production ramp-up and the delivery of production devices.
Under this engagement scenario, the customer has the capability of optionally performing their own scan insertion. All other aspects of the engagement will be identical to the RTL level engagement described above. |
