Development of Customer SoC projects is divided into five distinct phases. Project Preparation is the first phase which encompasses all aspects of design specifications. Exploration is the second phase in which the physical aspects of the design are explored. Trial layout, the third phase focuses on the performance of the design from a timing perspective. The fourth phase is the final layout process which addresses logical, physical, and performance aspects of the design. Photo Fabrication is the fifth and final phase bringing the project to completion. Details for each phase of the five stage process are provided below.

1. Project Preparation

This phase begins prior to the contract award date. At the end of this phase, all infrastructure and library related items will be in-place allowing the first RTL drop to be processed.

Some of the tasks included in the Project Preparation phase are as follows:

• IP and specialized pad-cell procurement
• Standard cell library preparation
• Memory generation and library preparation
• Pad library preparation
• IP library preparation
• Initiate package procurement
• Project CVS repository and directory preparation

2. Exploration

In this phase, the first RTL/SDC drop is processed, reviewed and feedback is provided to the Customer. RTL is assumed to be nearly 100% complete at this phase of the project. SDC is assumed to cover all relevant I/O pins and clocks, but may not cover all false-paths, MCPs and other functional design checks.

Some of the tasks included in the Exploration phase are as follows:

• First RTL/SDC drop is reviewed and processed with inSilica's physical synthesis flow. Any questions, comments or issues are reviewed with the Customer.
• Based on the first RTL/SDC drop, inSilica will generate the initial floor-plan that includes partitioning, power-planning, clock-planning and a die size estimate for Customer review.
• inSilica will develop the DFT chip micro-architecture and review it with the Customer. Any necessary RTL changes will be provided to the Customer at this time.
• Initial package selection and an overall project review with the Customer will be held at this time.

3. Trial Layout

This phase begins with the second RTL/SDC drop from the Customer. At this point in the project, RTL and SDC should be 100% functionally complete along with DFT. inSilica will begin the design implementation intensive efforts including place-and-route activities to drive RTL to GDS II flow. Taking RTL to a full trial tape-out including signoff verification, marks the completion of this phase

Some of the tasks included in the Trial Layout phase are as follows:

• Place and Route including timing closure for all blocks and the top-level of the design.
• Trial floor-plan and layout is reviewed with timing and congestion reports provided to Customer.
• Trial post-layout gate-level net-list with min/max SDFs will be delivered to Customer. Min/max SPEFs will be delivered upon request.
• Final package selection and an overall project review with the Customer will be held at this time.
• inSilica performs a fully simulated tape-out to fabrication including sign-off verification towards the end of this phase.

4. Final Layout

This phase begins with the third RTL/SDC drop from Customer. With the exception of minor ECOs, this drop should represent the final version of RTL/SDC, incorporating any appropriate changes to achieve timing convergence and address contention issues encountered during phase three, Trial Layout. These changes should be limited in scope and must not impact the design floor-plan. A major floor-plan change at this point in the project may require the design to revert back to the previous phase, Trial Layout.

Some of the tasks included in the Final Layout phase are as follows:

• RTL to GDS II sign-off verification with tape-out database ready for delivery to the fabricators.
• Final layout review with Customer.
• Final post-layout gate-level net-list and min/max SDFs will be delivered to Customer. Min/max SPEFs will be delivered upon request.
• ATPG vectors will be generated and results reviewed with the Customer.
• ATPG test-bench will be delivered to the Customer.
• A baseline of two ECO cycles is assumed for this phase of the project.
• For additional ECO iterations, the final ECO to tape-out latency will be approximately 2 weeks in duration.

5. Proto Fabrication

In this phase, the prototype parts are in fabrication.

Some of the tasks included in the Proto Fabrication phase are as follows:

• Wafer probes are ordered.
• Customer delivers functional test vectors.
• Wafer probe and package test program is developed.
• Test program is reviewed with Customer.
• Test program is debugged.
• Blind-build prototype delivery 1 week after wafer availability.
• Tested prototype delivery 2 to 4 weeks after wafer availability.