Customer SoC design projects will be developed under inSilica's RTL-handoff engagement model with the following division of responsibilities:

Customer Responsibilities:

• Customer will be responsible for the complete development, modification, maintenance and functional verification of the RTL.
• Customer will provide an SDC file that contains the complete constraints specifications for all primary I/Os, all generated clocks, any internal false-paths and multi-cycle paths.
• If requested by Customer, Customer will be responsible for all post-layout, gate-level logic simulations, with or without back-annotation. inSilica will provide the post-layout, gate-level net-list with min/max SDFs for back-annotation.
• Customer will provide simulation vectors for the purposes of functional test vector generation.
• Customer will provide a chip level specification that includes absolute max/min ratings, test conditions, and other information necessary to test and characterize the device.
• Customer will review and sign-off on package selection suggested by inSilica.

inSilica Responsibilities:

• inSilica will procure all third party IP cores needed for the design.
• inSilica will complete all necessary tasks to procure, characterize, and process the appropriate standard-cell library, pad-cell library, hard-macro libraries, memories (no memory repair capability is assumed for the device) and register files.
• inSilica will review, evaluate and make recommendations for RTL and SDC changes to accommodate DFT and other back-end related issues.
• inSilica will be responsible for the full RTL to tape-out flow. Some of the tasks include:
• Floor-planning, Power-planning, Power-analysis
• Scan and DFT Insertion
• Physical Synthesis
• Clock Tree Synthesis
• Place and Route with noise and EM avoidance/analysis
• ECO flow
• Spare Cells
• Filler Cells
• Timing Closure that includes noise delay effects
• DRC/ERC/LVS/Antenna
• Metal Fill/Slotting
• Formal equivalence checking
• GDS II generation
• Sign-off verification
• Gate-level net-list and SDF generation (SPEF upon request)
• inSilica will generate ATPG vectors to achieve at least 98% coverage of the un-collapsed, single-stuck-at, detectable faults in the random logic. Unobservable and uncontrollable faults will be excluded from the set of faults for the purposes of coverage calculation. Memories and register files will be covered using BIST.
• inSilica will be responsible for all tasks related to the ATE testing of the device. The tasks include the following
• Test program generation incorporating the ATPG vectors and the functional vectors supplied by Customer
• Test hardware development and procurement
• Wafer probing
• Package testing
• inSilica will be responsible for package selection and procurement. Customer will review and sign-off the package selected.
• inSilica will be responsible for prototype fabrication and delivery.
• inSilica will be responsible for the production ramp-up and the delivery of production parts.